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Lattice Semiconductor Announces ispClock5600 Programmable, Zero-Delay Clock Generator Devices
New High-Performance Devices Expand Existing ispClock Family,
Address Wider Range of Demanding Applications
HILLSBORO, Ore.—(BUSINESS WIRE)—Nov. 18, 2004—
Lattice Semiconductor Corporation (NASDAQ:LSCC) today announced
the addition of in-system programmable (ISP(TM)) zero-delay clock
generator devices to its revolutionary ispClock(TM) family. These new
ispClock5600 clock devices, while pin compatible with the recently
announced ispClock5500 devices, offer higher performance and
additional functionality. For example, the ispClock5600 devices
support external feedback for the PLL in order to support designs that
require the generated output clock(s) to be phase aligned with the
input clock. The first devices in the ispClock5600 family, the
10-output ispClock5610 and 20-output ispClock5620, combine a high-
performance clock generator with a flexible, Universal Fan-out Buffer.
The on-chip, zero-delay clock generator can provide up to 5 clock
frequencies, ranging from 10MHz to 320MHz, using a high-performance
PLL and clock multiply and divide facilities. The Universal Fan-out
Buffer can drive up to 20 clock nets using either single-ended or
differential signaling, with individual output control for improved
signal and timing integrity.
Additional Features Address Stringent Applications
The ispClock5600 devices are ideally suited for applications that
require local circuit board clocks to align their phases to a central
backplane clock (e.g., Advanced TCA, Medical Instrumentation, etc.),
or to distribute a master clock to a wide variety of ASICs and FPGAs
interfacing to the CPU Bus. Like the ispClock5500 family, these
devices use seven on-chip 5-bit counters (input, feedback, and five
output) to provide fine granularity output frequency selection. The
high-performance Universal Fan-out Buffer has a maximum pin-to-pin
skew of 50ps, regardless of bank and frequency, while the maximum
cycle-cycle (peak-peak) output jitter is less than 60ps, and the
period jitter is less than 10 ps (rms). The output skew of each clock
net relative to the reference input can be further controlled in delay
increments of 200ps (lead or lag) to compensate for differences in
circuit board clock network trace length. In addition, both the
reference input and the Universal Fan-out Buffers can support a wide
variety of popular single-ended and differential logic standards
(LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL) at a variety of voltage
levels. The input termination and output impedance of each output can
be individually tuned to match each trace impedance, resulting in
clock nets with high signal integrity.
"With the introduction of the ispClock5600 family, Lattice has
substantially increased its serviceable clock generator market," said
Stan Kopec, Lattice vice president of corporate marketing.
"Traditionally, as the performance requirements of the system
increased, the effort required to generate and distribute clocks grew
exponentially. The ispClock5600 devices provide unprecedented
convenience to designers without compromising the system
specifications, offering faster time to market and reduced board
space, as well as improved manufacturability and reliability."
Volume Production of the ispClock5510 Begins
Lattice has also announced that volume production of the second
member of the ispClock5500 family, the ispClock5510 device with 10
clock outputs in the 48-pin TQFP package, is underway. The ispClock
5510 joins the ispClock 5520, already in production, and is priced at
$10.75 in 1000 piece quantities.
PAC-Designer(R) Software
The Lattice PC-based mixed signal design tool, PAC-Designer
Version 3.2, provides comprehensive support for the ispClock5600
device family. In addition, utilities such as Graphical Skew Editor,
Frequency Calculator and Frequency Synthesis support have been
enhanced to address a wider range of application issues. Design
configurations can be downloaded quickly into ispClock5600 devices via
the PC parallel port. This version of the PAC-Designer software can be
downloaded for free from www.latticesemi.com.
Pricing and Availability
Prices for the first available device, the ispClock5620, start at
$21.90 in 1000 piece quantities. The ispClock5620 in a 100-pin TQFP
package is available immediately in both commercial (0C to +70C) and
industrial (-40C to +85C) temperature grades. PACsystemCLK5620
evaluation kits are also available through authorized Lattice
distributors or on the Lattice Web site for $295.
About ispClock Devices:
A Comprehensive Improvement Over Traditional Clock Network Design
Lattice is extending the benefits of integration, in-system
programmability and superior performance to clock management.
Historically, clock networks have been designed using multiple, simple
components -- such as fan-out buffers, clock generators, delay lines,
zero-delay buffers and frequency synthesizers -- with limited
functionality at various levels of the clock hierarchy. Timing errors
due to unequal PCB trace lengths have been addressed by using trace
length matching through serpentine trace layouts. Trace impedance
mismatch has been frequently mitigated by trial and error selection of
series resistors.
In contrast, ispClock devices are the first products that
conveniently and accurately solve the entire clock tree design problem
with a single chip. The ispClock devices compensate for timing errors
due to different trace length clock nets through a programmable skew
feature, match trace impedances with output impedances by programming
each output characteristic, and reduce EMI by programming output
switching speed or slew rate. This results in board space savings,
improved signal integrity, a simpler clock net hierarchy, improved
timing convergence and lower cost.
The ispClock devices' ability to store up to four timing and
output configurations and easily switch between them further extends
their utility by supporting easy clock margining (operating a circuit
board at higher than typical frequency to evaluate design robustness)
and power management (conserving dynamic power consumption by
"downshifting" to a more efficient, lower frequency when performance
is less critical). In-system programmability via the on-chip boundary
scan port helps debug complex timing problems and tune individual
network timing for best performance.
About Lattice Semiconductor
Lattice Semiconductor Corporation designs, develops and markets
the broadest range of Field Programmable Gate Arrays (FPGA), Field
Programmable System Chips (FPSC) and high-performance ISP(TM)
Programmable Logic Devices (PLD), including Complex Programmable Logic
Devices (CPLD), Programmable Analog Chips (PAC(TM)), and Programmable
Digital Interconnect (GDX(TM)). Lattice also offers industry leading
SERDES products. Lattice is "Bringing the Best Together" with
comprehensive solutions for today's system designs, delivering
innovative programmable silicon products that embody leading-edge
system expertise.
Lattice products are sold worldwide through an extensive network
of independent sales representatives and distributors, primarily to
OEM customers in the fields of communications, computing, computer
peripherals, instrumentation, industrial controls and military
systems. Company headquarters are located at 5555 NE Moore Court,
Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax
503-268-8037. For more information about Lattice Semiconductor
Corporation, visit http://www.latticesemi.com.
Statements in this news release looking forward in time are made
pursuant to the safe harbor provisions of the Private Securities
Litigation Reform Act of 1995. Investors are cautioned that
forward-looking statements involve risks and uncertainties including
market acceptance and demand for our new products, estimates of market
size and growth rate, our dependencies on our silicon wafer suppliers,
the impact of competitive products and pricing, technological and
product development risks and other risk factors detailed in the
Company's Securities and Exchange Commission filings. Actual results
may differ materially from forward-looking statements.
Lattice Semiconductor Corporation, Lattice (& design), L (&
design), GDX, ISP, ispClock, PAC, PAC-Designer and specific product
designations are either registered trademarks or trademarks of Lattice
Semiconductor Corporation or its subsidiaries in the United States
and/or other countries.
GENERAL NOTICE: Other product names used in this publication are
for identification purposes only and may be trademarks of their
respective holders.
Contact:
Lattice Semiconductor Corporation
Brian Kiernan, 503-268-8739
Fax: 503-268-8193
brian.kiernan@latticesemi.com
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